Method for forming aerial metallic wiring on semiconductor substrate

ABSTRACT

A temporary support layer  2  is formed on a semiconductor substrate  1,  and the temporary support layer  2  is provided with a hole  4  that reaches the semiconductor substrate  1.  The hole  4  is filled in with a conductor material  5,  and by pressurizing the conductor material  5,  the conductor material  5  and the semiconductor substrate  1  are pressure-bonded. Thereby, an aerial wiring structure whose bonding strength is improved and that has excellent self-sustainability can be obtained.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method for forming an aerialmetallic wiring in a fabricating process of a semiconductor typical inULSIs.

[0003] 2. Description of the Related Art

[0004] As a conventional technology relating to a method for forming anaerial metallic wiring, there is one, for instance, that is disclosed inJapanese Laid-open Application No. HEI 11-126820.

[0005] In this conventional method, an aerial wiring structure is formedin the following way. That is, a temporary film made of a carbon film isformed on a semiconductor substrate, a through-hole and a groove areformed in the temporary film, a Cu alloy film is deposited on thetemporary film according to a sputtering method, the Cu alloy film isreflowed by heat-treating at a temperature in the range of 400 to 500degree centigrade and filled in the groove and the through-hole, a plugfor burying the through-hole and a wiring connected to the plug andextending onto the temporary film are formed (hereinafter referred to as“a reflow method”), thereafter the temporary film is burned and removed,and thereby an aerial wiring structure made of a Cu alloy is formed onsemiconductor substrate.

[0006] In the conventional reflow method, since a bonding strengthbetween the plug and the semiconductor substrate is deficient and theplug and the semiconductor substrate are likely to peel off, there areproblems in that the aerial wiring may partially separate or an entiretythereof is likely to collapse.

[0007] Accordingly, the present invention intends to provide a methodfor forming an aerial metallic wiring in which a problem of bondingstrength deficiency between the conventional plug and the semiconductorsubstrate is overcome, the bonding strength is improved, and an aerialwiring structure having excellent self-sustainability can be formed.

SUMMARY OF THE INVENTION

[0008] In order to accomplish the above intentions, the presentinvention relies on the following measures. That is, the presentinvention relates to a method for forming an aerial metallic wiringabove a semiconductor substrate and includes the following steps: atemporary support layer is formed on the semiconductor substrate; a holethat penetrates through the temporary support layer and reaches thesemiconductor substrate is disposed in the temporary support layer; thehole is filled in with a conductor material; the conductor material ispressurized, and thereby the conductor material and the semiconductorsubstrate are pressure-bonded; and the aforementioned temporary supportlayer is removed, resulting in an aerial wiring structure in which theconductor material is self-sustained in a space above the semiconductorsubstrate.

[0009] According to the present invention, since the bonding isperformed according to the pressure bonding, in comparison with aconventional reflow method due to a reflow bonding, the bonding strengthbetween the conductor material and the semiconductor substrate can beimproved.

[0010] When a pressure is applied according to the present invention,the pressure is 30 MPa or more.

[0011] The application of the pressure is preferable to be hydrostaticpressurization.

[0012] The hydrostatic pressurization is preferably carried out in a gasatmosphere of a high temperature and a high pressure.

[0013] Still furthermore, the present invention may be configured so asto further include the following steps: after the disposition of thehole, a groove that communicates with the hole is disposed;simultaneously with filling in the hole with the conductor material, thegroove is filled in with the conductor material; and the conductormaterial in the hole and the semiconductor substrate are pressure-bondedfollowed by removing an excess conductor material positioned upward thanthe groove.

[0014] After the above aerial wiring structure is formed, a passivationlayer is preferably formed on a surface of the wiring structure tosuppress a surface diffusion phenomenon of the conductor material fromoccurring.

[0015] Prior to the pressurization, a passivation material may beinterposed between the temporary support layer and the conductormaterial to suppress causing a surface diffusion of the conductormaterial.

[0016] In order to form the aerial wiring structure into a multi-layeredone, after the conductor material in the hole and the semiconductorsubstrate are pressure-bonded, a second temporary support layer that hasa hole that extends to a underlying conductor material and is filled inwith a second conductor material is formed on the temporary supportlayer, the second conductor material is pressurized, and thereby thesecond conductor material and the conductor material underlyingthereunder are pressure-bonded.

[0017] According to the present invention, in a field of ULSIs that willbe furthermore forwarded in higher speed and miniaturization, an aerialwiring structure that is construed as an ultimate low dielectricconstant structure and a key to the higher speed can be fabricated overan entire wafer surface with a practically sufficient strength and witha high product yield.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIGS. 1A to 1G show process drawings showing a mode forimplementing the present invention.

[0019]FIGS. 2A to 2E show process drawings showing another mode forimplementing the present invention.

[0020]FIGS. 3A to 3E show process drawings showing still another modefor implementing the present invention.

[0021]FIG. 4 is a sectional view in which a passivation layer isarranged on a surface of an aerial wiring structure.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] In the following, with reference to the drawings, modes forimplementing the present invention will be explained.

[0023] What is shown in the present implementation mode relates to theformation of a metallic wiring structure having an aerial structure in afabricating process of a semiconductor typical in ULSIs. In particular,the present implementation mode relates to one in which by use of a PVDmethod, a CVD method, a plating method or a combination of the abovedeposition methods, a film of a wiring material is formed, and the filmof wiring material is pressurized in a gas atmosphere of a hightemperature and a high pressure (gas pressure annealing). According tothe process, a wiring film material can be filled in the hole or thegroove, and the bonding strength between the wiring layer of theunderlying semiconductor substrate and the wiring material filled in thehole portion can be improved, resulting in an aerial wiring structurehaving excellent self-sustainability.

[0024] In FIG. 1, a process for forming an aerial wiring structure isschematically shown with a one-layer wiring structure as a model.

[0025] In FIG. 1A, a temporary support layer 2 is formed on asemiconductor substrate 1.

[0026] The semiconductor substrate 1 is made of a silicon wafer andprovided with elements thereon.

[0027] The temporary support layer 2, when a structure of a conductorwiring is formed on the semiconductor substrate 1, works as a layer thatendows the conductor wiring with a shape and holds the same.

[0028] A material of the temporary support layer 2 may be aheat-disappearing material in an oxidizing atmosphere such as carbonshown in the aforementioned conventional technology, an organic materialelutable with a solvent such as an appropriate organic solvent or asuper-critical carbon dioxide gas, alternatively a silicon dioxide basedmaterial that can be removed with a fluorine based gas such ashydrofluoric acid.

[0029] However, when a heating step is included in an intermediateprocess other than the step of removing the temporary support layer 2,for instance, when the gas pressure annealing or the like is included,the material of the temporary support layer is required to have a stablemechanical strength necessary at the processing temperature.

[0030] Subsequently, as shown FIG. 1B, the temporary support layer 2 isprovided with a groove 3 formed on a surface thereof and a hole 4penetrating through in a thickness direction thereof. The particularhole 4 and groove 3 are communicated with each other.

[0031] The groove 3 is disposed to form an in-plane wiring, and the hole4 is disposed to form a column for connecting with an element such as atransistor and so on or a wiring layer of the underlying semiconductorsubstrate 1.

[0032] In the drawing, the groove 3 and the hole 4 are formed in onestep. Actually, since the groove 3 and the hole 4 are sequentiallyformed by use of an etching method that uses a mask formed of aphotoresist, two steps or more are necessary in many cases.

[0033] Next, as shown in FIG. 1C, the hole 4 and the groove 3, and asurface of the temporary support layer 2 are covered with a conductormaterial 5.

[0034] The formation of the conductor material 5 can be performed, byuse of a PVD method, a CVD method or a plating method, by covering asurface of the temporary support layer 2 therein the groove 3 and thehole 4 are formed with the conductor material 5.

[0035] Since it is natural that the conductor material 5 is preferableto be smaller in electrical resistance, a metal is usually used. Astypical conductor materials, Al (aluminum) and Cu (copper) or alloysmainly made thereof can be cited. In recent years, Cu that isadvantageous from a viewpoint of electrical resistance is widely used.In this case, in the covering and depositing, a PVD method or atwo-stage process is used. In the two-stage process, after an initialelectrode is formed according to the PVD method, an electroplatingmethod is used.

[0036] When these methods are used, in particular when the PVD method isused, since a deposition material is supplied as particles knocked outof a target consisting of a deposition material opposite to thesemiconductor substrate 1, when a depth is large relative to a diameterof an opening of the hole 4, it is difficult to form a dense film downto a bottom of the hole 4, or as shown in FIG. 1C, there frequentlyremains a portion (residual void 6) where the inside of the hole 4cannot be filled in with the conductor material 5. A shape of theresidual void 6, without restricting to spaces shown in FIG. 1C, may bea void in the conductor film material 5 as shown in FIG. 1G.

[0037] Accordingly, when the temporary support layer 2 is removed in alater step, there tends to occur problems in that the wiring structuremay not be connected with the underlying layer 1 or the wiring structuremay easily collapse.

[0038] Accordingly, not only the voids 6 occurring in this step, butalso factors that may cause a lower density and strength deficiencythereof are necessary to be removed. In particular, when the hole 4 isslender and deep, after the temporary support layer 2 is removed, thereremains a slender and long column. Accordingly, in particular, thestrength at a foot (bottom of the hole 4) and perfectness in the bondingwith the underlying layer are required.

[0039] Accordingly, as shown in FIG. 2D, in order to remove such aresidual void 6 mainly at the bottom of the hole 4 and to improve abonding strength with the underlying layer 1, a step of pressurizationis carried out.

[0040] In the pressurization, a surface of the conductor material 5 ispreferably pressurized with a hydrostatic pressure. The hydrostaticpressurization is carried out in a gas atmosphere under a hightemperature and a high pressure. As a pressurizing medium, an Ar gas isadequate.

[0041] In the pressurizing step (gas pressure annealing) with the hightemperature and high pressure gas, the conductor material 5 destined tobe a wiring is deformed according to a creep phenomenon and the residualvoid 6 is crushed, and at the same time, owing to a vertical directionstress applied at the bottom of the hole 4 at this time, diffusionbonding or an improvement in a close contact with the semiconductorsubstrate 1 is attained. Accordingly, conditions of the pressurizingprocess are different according to the conductor material 5 or thediameter and depth of the hole 4.

[0042] When, for instance, a diameter of the hole 4 is in the range of0.15 to 0.5 μm, a depth is substantially 1 μm, and the conductormaterial 5 is an aluminum alloy, a temperature in the range of 200 to450 degree centigrade, preferably 300 to 450 degree centigrade, apressure in the range of 30 to 100 MPa and a holding time in the rangeof substantially 10 to 300 seconds are sufficient.

[0043] Furthermore, in the case of the conductor material 5 being Cu,when the Cu is deposited by the ordinary PVD method alone, since thecreep phenomenon is difficult to occur, 450 to 500 degree centigrade,100 to 200 MPa and a holding time of 5 to 30 minute are necessary.However, though it is the same Cu, when the Cu film is formed by use ofthe electroplating or a PVD with added hydrogen, since a temperaturewhere the creep phenomenon occurs becomes lower, 350 to 450 degreecentigrade, 100 to 200 MPa and a holding time of substantially 5 to 15minute can cause an excellent bonding effect.

[0044] Then, as shown in FIG. 1E, the conductor material 5 of theportion upward than a surface of the temporary support layer 2, being inexcess, by use of chemical mechanical polishing method, is removed whilesecuring the flatness of the surface. Actually, although after thisstep, a furthermore upper layer is formed, an explanation thereof isomitted because this is a model structure.

[0045]FIG. 1F shows a state where the removal step of the temporarysupport layer 2 has come to completion and an aerial wiring 7 has beenformed. In the aerial wiring 7, a portion corresponding to the hole 4 isa column portion 8 and a portion corresponding to the groove 3 is awiring portion 9.

[0046] The method for removing the temporary support layer 2 isdifferent according to a material of the temporary support layer 2, anda method the same as the conventional method is used.

[0047] According to the aforementioned implementation mode of thepresent invention, owing to the gas pressure annealing step, theunderlying semiconductor substrate 1 and the in-plane wiring 7 formed inthe air are connected, and the strength of the holding column portion 8is secured. Accordingly, the wiring is hindered from coming off orcoming down.

[0048]FIGS. 2A through 2E show an example of a two-layered wiringstructure.

[0049] In FIG. 2A, on the semiconductor substrate gone through up to thestep shown in FIG. 1E, a second temporary support layer is formed.Following steps are fundamentally the same as those shown in FIG. 1.

[0050] That is, on the temporary support layer 2 gone through up to thestep shown in FIG. 1E, a second temporary support layer 10 is formed.The second temporary support layer 10 has a hole 11 that comes down tothe underlying conductor material 5 and a groove 12 (FIG. 2A).

[0051] The hole 11, the groove 12 and a surface of the second temporarysupport layer 10 are filled in with a second conductor material 13 (FIG.2B).

[0052] Subsequently, when the second conductor material 13 ispressurized, the second conductor material 13 and the underlyingconductor material 5 are pressure-bonded (FIG. 2C).

[0053] A material of the second temporary support layer 10 is the sameas that of the underlying temporary support layer 2. Furthermore, thesecond conductor material 12 is also the same as that of the underlyingconductor material 5.

[0054] Thereafter, the second conductor material 12 upward than thesecond temporary support layer 10 is removed by use of the CMP methodand is planarized (FIG. 2D).

[0055] Then, the underlying temporary support layer 2 and the secondtemporary support layer 10 are removed in the method similar to theconventional one, and thereby a two-layered aerial wiring 14 can beobtained.

[0056] In this case, in order to eliminate the residual voids at thebottom of the hole 11, the gas pressure annealing is performed. Whensuch the multi-layered structure is taken, when the structure is simplesuch as that the holes 4 and 11 are located in the substantially samepositions through an entire layers, only one gas pressure annealingprocess after the formation of the last wiring may collectivelyeliminate the residual voids at the bottoms of the underlying holes 4.

[0057] Furthermore, an aerial wiring structure having a multi-layeredstructure more than two layers also can be obtained according to astacking method similar to the above.

[0058]FIG. 3 illustrates an example in which it is utilized that whenthe gas pressure annealing is used, even when the bottom portion of thehole 4 is structured expanded than an opening thereof, the conductormaterial 5 can be filled in owing to the creep phenomenon.

[0059] Specifically, when the column portion 8 is finally formed andsupports an entire wiring structure, the column portion 8 is necessaryto have a mechanical strength at the foot thereof 8. Accordingly, inorder to make a contact area larger in the neighborhood of the bottom ofthe hole 4, the hole is formed into an inverse tapered shape. Even whenthe hole 4 is thus structured, as shown in FIG. 3C, the conductormaterial 5 is pushed into an entirety of the hole 4 owing to thepressure, resulting in the elimination of the residual voids 6.

[0060]FIG. 4 shows a method of hindering disconnection resulting fromdiffusion of a flow of electrons of conductor atoms due toelectromigration (EM) phenomenon that is anxious in the actual aerialwiring 7.

[0061] The diffusion of the conductor atoms is said to be mainly asurface diffusion and is likely to occur when a surface is exposed to anair or a vacuum. Accordingly, in order to suppress the surface diffusionfrom occurring, the conductor material is preferable to be covered witha film of a stable material (passivation film 15) that is non-reactivewith the conductor material 5. As a material of the passivation film 15like this, a SiN based insulating film (deposited with silane andammonia as raw material gases) can be cited as a typical example. Whenit is an electrically insulating material, even when the film is formeddown to a Si substrate 1 at the lower-most layer, there is no anxiety ofoccurrence of electrical dielectric breakdown or the like. Furthermore,the function of the passivation has an effect of suppressing aninfluence of an ambient atmosphere, for instance, of humidity or thelike.

[0062] The formation of the passivation film 15 is realized by, afterthe formation of the hole 4 and the groove 3 in the temporary supportlayer 2, covering the insides of the hole 4 and the groove 3 by use ofthe CVD method or the like.

[0063] Furthermore, as a method of forming the passivation layer on anentire aerial wiring structure, there is a method of depositing a filmafter the aerial wiring 7 is formed.

[0064] That is, after the aerial wiring 7 is formed according to theaforementioned method, the passivation film 15 is given with adeposition technique. Since it is preferable to form on an entiresurface of the conductor structure, the use of the CVD method isrecommended

Embodiments

[0065] In the following, embodiments of the present invention will beexplained.

[0066] Embodiment 1 and Comparative Embodiment 1

[0067] On each of two Si wafers (semiconductor substrate 1) on each ofwhich as a temporary support layer 2 a SiO₂ film (thickness: 2 μm) witha hole 4 (diameter: 0.25 μm) was formed, a TaN layer was formed with athickness of 50 nm at a surface of the wafer followed by the formationof a seed layer for use in electroplating having a thickness of 150 nmby use of the PVD method.

[0068] Subsequently, as a conductor material 5, a Cu layer having athickness of 1.5 μm is formed by use of the electroplating method. Oneof the two wafers underwent an ordinary annealing in a reduced pressureatmosphere electric furnace in a nitrogen atmosphere at 400 degreecentigrade for 30 min (Comparative Embodiment 1), and the other oneunderwent the gas pressure annealing according to the present inventionat the same temperature of 400 degree centigrade, and 150 MPa(Embodiment 1).

[0069] An excess Cu layer on a surface of each of the wafers was removedby use of the CMP method followed by processing with a hydrogen fluoridegas, and thereby the SiO₂ layer of the temporary support layer 2 wasremoved.

[0070] When the wafers were observed after the removal of the SiO₂layer, it was confirmed that while in the ordinarily annealed one(Comparative Embodiment 1), Cu of a column portion 8 (cylindrical rod)hardly remained except a wafer center portion, in the gas pressureannealed one (Embodiment 1), Cu of the column portion 8 regularly stoodup.

[0071] Embodiment 2 and Comparative Embodiment 2

[0072] Two sample wafers each of which had the model structure shown inFIG. 1 (diameter of the hole 4: 0.25 μm, depth: 0.65 μm, width of thegroove 3: 0.4 μm, and depth: 0.5 μm) were prepared. For a material ofthe temporary support layer 2, carbon obtained by coating phenolic resinfollowed by a thermal process was used. Except for the formation of theTaN layer and the seed film, other than that an entire Cu film wasformed by means of the electroplating, a method similar to that ofEmbodiment 1 and Comparative Embodiment 1 was employed.

[0073] After an excess Cu was removed by use of the CMP method, thesamples were heated in air with a temperature rise speed of 5 degreecentigrade an hour from 300 to 550 degree centigrade followed by holdingthere for 1 hr. The obtained samples were observed.

[0074] In the ordinarily annealed sample (Comparative Embodiment 2),although the aerial wiring structures were confirmed at severalpositions of the wafer center, the wiring structure sufficiently formedover the entire wafer surface could not be obtained.

[0075] On the other hand, in the gas pressure annealed sample(Embodiment 2), it was confirmed that the aerial wiring structuresubstantially the same as that shown in FIG. 1F was formed over asubstantially entire wafer surface.

[0076] The present invention is not restricted to ones shown in theabove implementation modes and Embodiments.

What is claimed is:
 1. A method of forming an aerial metallic wiring ona semiconductor substrate, comprising: forming a temporary support layeron a semiconductor substrate; disposing a hole that penetrates throughthe temporary support layer and reaches the semiconductor substrate inthe temporary support layer; filling in the hole with a conductormaterial; pressurizing the conductor material, and therebypressure-bonding the conductor material and the semiconductor substrate;and removing the temporary support layer, and thereby forming theconductor material into an aerial wiring structure that isself-sustained in a space above the semiconductor substrate.
 2. Themethod of forming an aerial metallic wiring as set forth in claim 1,wherein a pressure at the pressurizing is 30 MPa or more.
 3. The methodof forming an aerial metallic wiring as set forth in claim 1, furthercomprising: disposing, after the disposition of the hole, a groove thatcommunicates with the hole; filling in the hole with the conductormaterial and at the same time filling in the groove with the conductormaterial; and after the conductor material in the hole and thesemiconductor substrate are pressure-bonded, an excess conductormaterial in a upper portion than the groove is removed.
 4. The method offorming an aerial metallic wiring as set forth in claim 1, wherein thepressurizing is hydrostatic pressurizing.
 5. The method of forming anaerial metallic wiring as set forth in claim 4, wherein the hydrostaticpressurizing is performed in a gas atmosphere of a high temperature anda high pressure.
 6. The method of forming an aerial metallic wiring asset forth in claim 5, wherein the hydrostatic pressurizing is performedat a temperature of 200 degree centigrade or more.
 7. The method offorming an aerial metallic wiring as set forth in claim 1, furthercomprising: after the removal of the temporary support layer, forming asecond temporary support layer on the temporary support layer;disposing, in the second temporary support layer, a second hole thatreaches an underlying conductor material; filling in the second holewith a second conductor material; and pressurizing the second conductormaterial and thereby pressure-bonding the second conductor material andthe underlying conductor material.
 8. The method of forming an aerialmetallic wiring as set forth in claim 1, further comprising: forming apassivation layer on the inner surface of the hole, after thedisposition of the hole and before filling the hole with the conductormaterial.
 9. The method of forming an aerial metallic wiring as setforth in claim 3, further comprising: forming a passivation layer on theinner surface of the hole, after the disposition of the hole and thegroove and before filling the hole and the groove with the conductormaterial.